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an important notice at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. advance information for pre-production products; subject to change without notice. LM5122ZA snvsb54 ? may 2018 LM5122ZA wide-input synchronous boost controller with multiple phase capability 1 1 features 1 ? maximum input voltage: 65 v ? minimum input voltage: 3 v (4.5 v for start-up) ? output voltage up to 100 v ? bypass (v out = v in ) operation ? 1.2-v reference with 1% accuracy ? free-run and synchronizable switching to 1 mhz ? peak-current-mode control ? robust 3-a integrated gate drivers ? adaptive dead-time control ? optional diode-emulation mode ? programmable cycle-by-cycle current limit ? hiccup-mode overload protection ? programmable line uvlo ? programmable soft start ? thermal shutdown protection ? low shutdown quiescent current: 9 a ? programmable slope compensation ? programmable skip-cycle mode reduces standby power ? allows external vcc supply ? inductor dcr current sensing capability ? multi-phase capability ? thermally enhanced 24-pin htssop 2 applications ? 12-v, 24-v, and 48-v power systems ? wireless infrastructure ? audio power supply ? high-current boost power supply 3 description the LM5122ZA is a multi-phase capable synchronous boost controller intended for high- efficiency synchronous boost regulator applications. the control method is based upon peak-current-mode control. current-mode control provides inherent line feed forward, cycle-by-cycle current limiting, and ease of loop compensation. the switching frequency is programmable up to 1 mhz. higher efficiency is achieved by two robust n- channel mosfet gate drivers with adaptive dead- time control. a user-selectable diode-emulation mode also enables discontinuous-mode operation for improved efficiency at light load conditions. an internal charge pump allows 100% duty cycle for high-side synchronous switch (bypass operation). a 180 phase shifted clock output enables easy multi- phase interleaved configuration. additional features include thermal shutdown, frequency synchronization, hiccup-mode current limit, and adjustable line undervoltage lockout. device information (1) part number package body size (nom) LM5122ZA htssop (24) 7.80 mm 4.40 mm (1) for all available packages, see the orderable addendum at the end of the data sheet. space space simplified application diagram vcc LM5122ZA csp syncin/rt res ss uvlo vin syncout agnd bst mode pgnd slope comp fb ho lo sw + opt v out csn v in copyright ? 2017, texas instruments incorporated advance information tools & software technical documents ordernow productfolder support &community
2 LM5122ZA snvsb54 ? may 2018 www.ti.com product folder links: LM5122ZA submit documentation feedback copyright ? 2018, texas instruments incorporated table of contents 1 features .................................................................. 1 2 applications ........................................................... 1 3 description ............................................................. 1 4 revision history ..................................................... 2 5 pin configuration and functions ......................... 3 6 specifications ......................................................... 5 6.1 absolute maximum ratings ...................................... 5 6.2 esd ratings .............................................................. 5 6.3 recommended operating conditions ....................... 6 6.4 thermal information ................................................. 6 6.5 electrical characteristics ........................................... 6 6.6 typical characteristics ............................................ 10 7 detailed description ............................................ 13 7.1 overview ................................................................. 13 7.2 functional block diagram ....................................... 13 7.3 feature description ................................................. 14 7.4 device functional modes ........................................ 21 8 application and implementation ........................ 24 8.1 application information ............................................ 24 8.2 typical application .................................................. 34 9 power supply recommendations ...................... 43 10 layout ................................................................... 43 10.1 layout guidelines ................................................. 43 10.2 layout example .................................................... 43 11 device and documentation support ................. 44 11.1 trademarks ........................................................... 44 11.2 electrostatic discharge caution ............................ 44 11.3 glossary ................................................................ 44 12 mechanical, packaging, and orderable information ........................................................... 44 4 revision history date revision notes may 2018 * advance information release. advance information
3 LM5122ZA www.ti.com snvsb54 ? may 2018 product folder links: LM5122ZA submit documentation feedback copyright ? 2018, texas instruments incorporated (1) g = ground, i = input, o = output, p = power 5 pin configuration and functions pwp package 24-pin htssop with exposed pad top view pin functions pin type (1) description name no. agnd 11 g \\analog ground connection. return for the internal voltage reference and\ analog circuits. bst 24 p high-side driver supply for bootstrap gate drive. connect to the cathode of the external bootstrap diode and to the bootstrap capacitor. the bootstrap capacitor supplies current to charge the high-side n-channel mosfet gate and should be placed as close to controller as possible. an internal bst charge pump supplies 200- a current into bootstrap capacitor for bypass operation. comp 13 o output of the internal error amplifier. connect the loop compensation network between this pin and the fb pin. csn 4 i inverting input of current sense amplifier. connect to the negative-side of the current sense resistor. csp 5 i non-inverting input of current sense amplifier. connect to the positive-side of the current sense resistor. fb 12 i feedback. inverting input of the internal error amplifier. a resistor divider from the output to this pin sets the output voltage level. the regulation threshold at the fb pin is 1.2 v. the controller is configured as slave mode if the fb pin voltage is above 2.7 v at initial power-on. ho 23 o high-side n-channel mosfet gate drive output. connect to the gate of the high-side synchronous n-channel mosfet switch through a short, low inductance path. lo 18 o low-side n-channel mosfet gate drive output. connect to the gate of the low-side n- channel mosfet switch through a short, low inductance path. mode 15 i switching mode selection pin. 700-k pullup and 100-k pulldown resistor internal hold mode pin to 0.15 v as a default. by adding external pullup or pulldown resistor, mode pin voltage can be programmed. when mode pin voltage is greater than 1.2-v diode emulation mode threshold, forced pwm mode is enabled, allowing current to flow in either direction through the high-side n-channel mosfet switch. when mode pin voltage is less than 1.2 v, the controller works in diode emulation mode. skip cycle comparator is activated as a default. if mode pin is grounded, the controller still operates in diode emulation mode, but the skip cycle comparator will not be triggered in normal operation, this enables pulse skipping operation at light load. advance information syncout vin opt nc csn csp res uvlo syncin/rt bst mode lo sw nc ho vcc nc ss nc 16 23 4 5 8 9 24 18 19 23 22 21 20 17 16 15 ep pgnd 10 7 slope fb comp agnd 11 14 13 12
4 LM5122ZA snvsb54 ? may 2018 www.ti.com product folder links: LM5122ZA submit documentation feedback copyright ? 2018, texas instruments incorporated pin functions (continued) pin type (1) description name no. opt 2 i clock synchronization selection pin. this pin also enables/disables syncout related with master/slave configuration. the opt pin should not be left floating. pgnd 17 g power ground connection pin for low-side n-channel mosfet gate driver. connect directly to the source terminal of the low-side n-channel mosfet switch. res 16 o the restart timer pin for an external capacitor that configures hiccup mode off-time and restart delay during over load conditions. connect directly to the agnd when hiccup mode operation is not required. slope 14 i slope compensation is programmed by a single resistor between slope and the agnd. ss 9 i soft-start programming pin. an external capacitor and an internal 10- a current source set the ramp rate of the internal error amplifier reference during soft-start. sw 22 i/o switching node of the boost regulator. connect to the bootstrap capacitor, the source terminal of the high-side n-channel mosfet switch and the drain terminal of the low-side n- channel mosfet switch through short, low inductance paths. syncin/rt 10 i the internal oscillator frequency is programmed by a single resistor between rt and the agnd. the internal oscillator can be synchronized to an external clock by applying a positive pulse signal into this syncin pin. the recommended maximum internal oscillator frequency in master configuration is 2 mhz which leads to 1 mhz maximum switching frequency. syncout 1 o clock output pin. syncout provides 180 shifted clock output for an interleaved operation. syncout pin can be left floating when it is not used. see slave mode and syncout section. uvlo 8 i undervoltage lockout programming pin. if the uvlo pin is below 0.4 v, the regulator is in the shutdown mode with all functions disabled. if the uvlo pin voltage is greater than 0.4 v and below 1.2 v, the regulator is in standby mode with the vcc regulator operational and no switching at the ho and lo outputs. if the uvlo pin voltage is above 1.2 v, the start-up sequence begins. a 10- a current source at uvlo pin is enabled when uvlo exceeds 1.2 v and flows through the external uvlo resistors to provide hysteresis. the uvlo pin should not be left floating. vcc 19 p/o/i vcc bias supply pin. locally decouple to pgnd using a low esr/esl capacitor located as close as possible to controller. vin 6 p/i supply voltage input source for the vcc regulator. connect to input capacitor and source power supply connection with short, low impedance paths. ep n/a exposed pad of the package. no internal electrical connections. must be soldered to the large ground plane to reduce thermal resistance. nc 3, 7, 20, 21 no electrical contact advance information
5 LM5122ZA www.ti.com snvsb54 ? may 2018 product folder links: LM5122ZA submit documentation feedback copyright ? 2018, texas instruments incorporated (1) stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions are not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. unless otherwise specified, all voltages are referenced to agnd pin. (2) see application and implementation when input supply voltage is less than the vcc voltage. (3) all output pins are not specified to have an external voltage applied. 6 specifications 6.1 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) (1) min max unit input vin, csp, csn ? 0.3 75 v bst to sw, fb, mode, uvlo, opt, vcc (2) ? 0.3 15 v sw ? 5 105 v bst ? 0.3 115 v ss, slope, syncin/rt ? 0.3 7 v csp to csn, pgnd ? 0.3 0.3 v output (3) ho to sw ? 0.3 bst to sw + 0.3 v lo ? 0.3 vcc + 0.3 v comp, res, syncout ? 0.3 7 v thermal junction temperature, t j ? 40 150 c storage temperature, t stg ? 55 150 c (1) jedec document jep155 states that 500-v hbm allows safe manufacturing with a standard esd control process. (2) jedec document jep157 states that 250-v cdm allows safe manufacturing with a standard esd control process. 6.2 esd ratings value unit v (esd) electrostatic discharge human body model (hbm), per jesd22-a114 (1) 2000 v charged device model (cdm), per jesd22-c101 (2) 1000 advance information
6 LM5122ZA snvsb54 ? may 2018 www.ti.com product folder links: LM5122ZA submit documentation feedback copyright ? 2018, texas instruments incorporated (1) recommended operating conditions are conditions under which operation of the device is intended to be functional, but do not ensure specific performance limits. (2) minimum vin operating voltage is always 4.5 v. the minimum input power supply voltage can be 3 v after start-up, assuming vin voltage is supplied from an available external source. 6.3 recommended operating conditions over operating free-air temperature range (unless otherwise noted) (1) min max unit input supply voltage (2) vin 4.5 65 v low-side driver bias voltage vcc 14 v high-side driver bias voltage bst to sw 3.8 14 v current sense common mode range (2) csp, csn 3 65 v switch node voltage sw 100 v junction temperature, t j ? 40 125 c (1) for more information about traditional and new thermal metrics, see the semiconductor and ic package thermal metrics application report. 6.4 thermal information thermal metric (1) LM5122ZA unit pwp (htssop) 24 pins r ja junction-to-ambient thermal resistance 32.4 c/w r jc(top) junction-to-case (top) thermal resistance 15.6 c/w r jb junction-to-board thermal resistance 7.5 c/w jt junction-to-top characterization parameter 0.2 c/w jb junction-to-board characterization parameter 7.7 c/w r jc(bot) junction-to-case (bottom) thermal resistance 1.1 c/w 6.5 electrical characteristics unless otherwise specified, these specifications apply for ? 40 c t j +125 c, v vin = 12 v, v vcc = 8.3 v, r t = 20 k ? , no load on lo and ho. typical values represent the most likely parametric norm at t j = 25 c and are provided for reference purposes only. parameter test conditions min typ max unit vin supply i shutdown vin shutdown current v uvlo = 0 v 9 17 a i bias vin operating current (exclude the current into rt resistor) v uvlo = 2 v, non-switching 4 5 ma vcc regulator v cc(reg) vcc regulation no load 6.9 7.6 8.3 v vcc dropout (vin to vcc) v vin = 4.5 v, no external load 0.25 v v vin = 4.5 v, i vcc = 25 ma 0.28 0.5 v vcc sourcing current limit v vcc = 0 v 50 62 ma i vcc vcc operating current (exclude the current into rt resistor) v vcc = 8.3 v 3.5 5 ma v vcc = 12 v 4.5 8 ma vcc undervoltage threshold vcc rising, v vin = 4.5 v 3.9 4 4.1 v vcc falling, v vin = 4.5 v 3.7 v vcc undervoltage hysteresis 0.385 v undervoltage lockout uvlo threshold uvlo rising 1.17 1.2 1.23 v uvlo hysteresis current v uvlo = 1.4 v 7 10 13 a uvlo standby enable threshold uvlo rising 0.3 0.4 0.5 v uvlo standby enable hysteresis 0.1 0.125 v advance information
7 LM5122ZA www.ti.com snvsb54 ? may 2018 product folder links: LM5122ZA submit documentation feedback copyright ? 2018, texas instruments incorporated electrical characteristics (continued) unless otherwise specified, these specifications apply for ? 40 c t j +125 c, v vin = 12 v, v vcc = 8.3 v, r t = 20 k ? , no load on lo and ho. typical values represent the most likely parametric norm at t j = 25 c and are provided for reference purposes only. parameter test conditions min typ max unit mode diode emulation mode threshold mode rising 1.2 1.24 1.28 v diode emulation mode hysteresis 0.1 v default mode voltage 145 155 170 mv default skip cycle threshold comp rising, measured at comp 1.290 v comp falling, measured at comp 1.245 v skip cycle hysteresis measured at comp 40 mv error amplifier v ref fb reference voltage measured at fb, v fb = v comp 1.188 1.2 1.212 v fb input bias current v fb = v ref 5 na v oh comp output high voltage i source = 2 ma, v vcc = 4.5 v 2.75 v i source = 2 ma, v vcc = 12 v 3.4 v v ol comp output low voltage i sink = 2 ma 0.25 v a ol dc gain 80 db f bw unity gain bandwidth 3 mhz slave mode threshold fb rising 2.7 3.4 v oscillator f sw1 switching frequency 1 r t = 20 k ? 400 450 500 khz f sw2 switching frequency 2 r t = 10 k ? 775 875 975 khz rt output voltage 1.2 v rt sync rising threshold rt rising 2.5 2.9 v rt sync falling threshold rt falling 1.6 2 v minimum sync pulse width 100 ns syncout syncout high-state voltage i syncout = ? 1 ma 3.3 4.3 v syncout low-state voltage i syncout = 1 ma 0.15 0.25 v opt synchronization selection threshold opt rising 2 3 4 v slope compensation slope output voltage 1.17 1.2 1.23 v v slope slope compensation amplitude r slope = 20 k ? , f sw = 100 khz, 50% duty cycle, t j = ? 40 c to 125 c 1.375 1.65 1.925 v r slope = 20 k ? , f sw = 100 khz, 50% duty cycle, t j = 25 c 1.4 1.65 1.9 v soft start i ss-source ss current source v ss = 0 v 7.5 10 12 a ss discharge switch r ds-on 13 pwm comparator t lo-off forced lo off-time v vcc = 5.5 v 330 400 ns v vcc = 4.5 v 560 750 ns t on-min minimum lo on-time r slope = 20 k ? 150 ns r slope = 200 k ? 300 ns comp to pwm voltage drop t j = ? 40 c to 125 c 0.95 1.1 1.25 v t j = 25 c 1 1.1 1.2 v advance information
8 LM5122ZA snvsb54 ? may 2018 www.ti.com product folder links: LM5122ZA submit documentation feedback copyright ? 2018, texas instruments incorporated electrical characteristics (continued) unless otherwise specified, these specifications apply for ? 40 c t j +125 c, v vin = 12 v, v vcc = 8.3 v, r t = 20 k ? , no load on lo and ho. typical values represent the most likely parametric norm at t j = 25 c and are provided for reference purposes only. parameter test conditions min typ max unit current sense / cycle-by-cycle current limit v cs-th1 cycle-by-cycle current limit threshold csp to csn, t j = ? 40 c to 125 c 65.5 75 87.5 mv csp to csn, t j = 25 c 67 75 86 mv v cs-zcd zero cross detection threshold csp to csn, rising 7 mv csp to csn, falling 0.5 6 12 mv current sense amplifier gain 10 v/v i csp csp input bias current 12 a i csn csn input bias current 11 a bias current matching i csp ? i csn ? 2.5 1 8.75 a cs to lo delay current sense / current limit delay 150 ns hiccup-mode restart v res restart threshold res rising 1.15 1.2 1.25 v v hcp- upper hiccup counter upper threshold res rising 4.2 v res rising, v vin = v vcc = 4.5 v 3.6 v v hcp- lower hiccup counter lower threshold res falling 2.15 v res falling, v vin = v vcc = 4.5 v 1.85 v i res- source1 res current source1 fault-state charging current 20 30 40 a i res-sink1 res current sink1 normal-state discharging current 5 a i res- source2 res current source2 hiccup-mode off-time charging current 10 a i res-sink2 res current sink2 hiccup-mode off-time discharging current 5 a hiccup cycle 8 cycles res discharge switch r ds-on 40 ratio of hiccup mode off-time to restart delay time 122 ho gate driver v ohh ho high-state voltage drop i ho = ? 100 ma, v ohh = v bst ? v ho 0.15 0.24 v v olh ho low-state voltage drop i ho = 100 ma, v olh = v ho ? v sw 0.1 0.18 v ho rise time (10% to 90%) c load = 4700 pf, v bst = 12 v 25 ns ho fall time (90% to 10%) c load = 4700 pf, v bst = 12 v 20 ns i ohh peak ho source current v ho = 0 v, v sw = 0 v, v bst = 4.5 v 0.8 a v ho = 0 v, v sw = 0 v, v bst = 7.6 v 1.9 a i olh peak ho sink current v ho = v bst = 4.5 v 1.9 a v ho = v bst = 7.6 v 3.2 a i bst bst charge pump sourcing current v vin = v sw = 9. v , v bst - v sw = 5 v 100 200 a bst charge pump regulation b st to sw, i bst = ? 70 a, v vin = v sw = 9 v 5.3 6.2 6.75 v b st to sw, i bst = ? 70 a, v vin = v sw = 12 v 7 8.5 9 v bst to sw undervoltage 2 3 3.5 v bst dc bias current v bst ? v sw = 12 v, v sw = 0 v 30 45 a advance information
9 LM5122ZA www.ti.com snvsb54 ? may 2018 product folder links: LM5122ZA submit documentation feedback copyright ? 2018, texas instruments incorporated electrical characteristics (continued) unless otherwise specified, these specifications apply for ? 40 c t j +125 c, v vin = 12 v, v vcc = 8.3 v, r t = 20 k ? , no load on lo and ho. typical values represent the most likely parametric norm at t j = 25 c and are provided for reference purposes only. parameter test conditions min typ max unit lo gate driver v ohl lo high-state voltage drop i lo = ? 100 ma, v ohl = v vcc ? v lo 0.15 0.25 v v oll lo low-state voltage drop i lo = 100 ma, v oll = v lo 0.1 0.17 v lo rise time (10% to 90%) c load = 4700 pf 25 ns lo fall time (90% to 10%) c load = 4700 pf 20 ns i ohl peak lo source current v lo = 0 v, v vcc = 4.5 v 0.8 a v lo = 0 v 2 a i oll peak lo sink current v lo = v vcc = 4.5 v 1.8 a v lo = v vcc 3.2 a switching characteristics t dlh lo fall to ho rise delay no load, 50% to 50% 50 80 145 ns t dhl ho fall to lo rise delay no load, 50% to 50% 60 80 105 ns thermal t sd thermal shutdown temperature rising 165 c thermal shutdown hysteresis 25 c advance information
10 LM5122ZA snvsb54 ? may 2018 www.ti.com product folder links: LM5122ZA submit documentation feedback copyright ? 2018, texas instruments incorporated 6.6 typical characteristics figure 1. ho peak current vs v bst - v sw figure 2. lo peak current vs v vcc figure 3. dead time vs v vcc figure 4. dead time vs temperature figure 5. dead time vs v sw figure 6. i shutdown vs temperature 0.00 1.00 2.00 3.00 4.00 5.00 6.00 4 5 6 7 8 9 10 11 12 13 14 lo peak current [a] v vcc [v] c001 v vin = 12v source sink 50 55 60 65 70 75 80 85 90 95 100 -50 -25 0 25 50 75 100 125 150 dead-time [ns] temperature [ ? c] c001 t dhl t dlh 0.00 1.00 2.00 3.00 4.00 5.00 4 5 6 7 8 9 10 11 12 13 14 ho peak current [a] v bst - v sw [v] c001 v vin = 12v v sw = 0v source sink 0.0 10.0 20.0 30.0 40.0 50.0 60.0 70.0 80.0 90.0 100.0 0 10 20 30 40 50 60 dead-time [ns] v sw [v] c001 v vin = 12v v vcc = 7.6v cload=2600pf 1v to 1v t dlh t dhl 0.00 10.00 20.00 30.00 40.00 50.00 60.00 70.00 80.00 90.00 100.00 4 5 6 7 8 9 10 11 12 dead-time [ns] v vcc [v] c001 v vin = 12v v sw = 12v c load =2600pf 1v to 1v t dlh t dhl advance information 0 5 10 15 20 -50 -25 0 25 50 75 100 125 150 i shutdown [ p a] temperature [ ? c] c001
11 LM5122ZA www.ti.com snvsb54 ? may 2018 product folder links: LM5122ZA submit documentation feedback copyright ? 2018, texas instruments incorporated typical characteristics (continued) figure 7. v vcc vs i vcc figure 8. v vcc vs v vin figure 9. error amplifier gain and phase vs frequency figure 10. i csp , i csn vs temperature figure 11. v bst-sw vs v sw figure 12. i bst vs temperature 0.0 5.0 10.0 15.0 4 9 14 19 v bst-sw [v] v sw [v] c001 i bst = -70ua advance information 0 2 4 6 8 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 v vcc [v] v vin [v] c001 no load 0 2 4 6 8 0 10 20 30 40 50 60 70 80 v vcc [v] i vcc [ma] c001 no load -45 0 45 90 135 180 -10 0 10 20 30 40 1000 10000 100000 1000000 10000000 gain [db] frequency [hz] c002 phase gain a cl =101, comp unload phase [] 0 5 10 15 -50 -25 0 25 50 75 100 125 150 i csp, i csn [ p a] temperature [ ? c] c001 i csp i csn 100 120 140 160 180 200 220 240 260 280 300 -50 -25 0 25 50 75 100 125 150 bst charging current [ p a] temperature [ ? c] c001 v vin =v sw =9v
12 LM5122ZA snvsb54 ? may 2018 www.ti.com product folder links: LM5122ZA submit documentation feedback copyright ? 2018, texas instruments incorporated typical characteristics (continued) figure 13. v cs-th1 vs v vin figure 14. v cs-th1 vs temperature figure 15. v bst-sw vs temperature 70 75 80 4 5 6 7 8 9 10 11 12 v cs-th1 [mv] v vin [v] c001 v vin =v csp 0.00 1.00 2.00 3.00 4.00 5.00 6.00 7.00 8.00 9.00 10.00 11.00 12.00 -50 -25 0 25 50 75 100 125 150 v bst-sw [v] temperature [ ? c] c001 v sw = 12v v sw = 9v v vin = v sw i bst = -70ua advance information 60 65 70 75 80 85 90 -50 -25 0 25 50 75 100 125 150 v cs-th1 [mv] temperature [ ? c] c001
13 LM5122ZA www.ti.com snvsb54 ? may 2018 product folder links: LM5122ZA submit documentation feedback copyright ? 2018, texas instruments incorporated 7 detailed description 7.1 overview the LM5122ZA wide input range synchronous boost controller features all of the functions necessary to implement a highly efficient synchronous boost regulator. the regulator control method is based upon peak- current-mode control. peak-current-mode control provides inherent line feedforward and ease of loop compensation. this highly integrated controller provides strong high-side and low-side n-channel mosfet drivers with adaptive dead-time control. the switching frequency is user programmable up to 1 mhz set by a single resistor or synchronized to an external clock. the 180 o -shifted clock output of the LM5122ZA enables easy multi-phase configuration. the control mode of high-side synchronous switch can be configured as either forced pwm (fpwm) or diode- emulation mode. fault protection features include cycle-by-cycle current limiting, hiccup-mode overload protection, thermal shutdown and remote shutdown capability by pulling down the uvlo pin. the uvlo input enables the controller when the input voltage reaches a user selected threshold, and provides a tiny 9- a shutdown quiescent current when pulled low. the device is available in a 24-pin htssop package featuring an exposed pad to aid in thermal dissipation. 7.2 functional block diagram advance information 0.4v/0.3v shutdown 10 ua uvlo + - + - standby 1.2 v clk s r qq + - + - 750 mv pwm comparator c/l comparator vcc regulator vcc pgnd vcc level shift diode emulation bst ho sw lo adaptive timer pwm + - zcd threshold + - csn cs amp 1.2 v 1.2 v + + - fb comp err amp -+ lm 5122 za csp ss 10 ua r estart t imer res 30 ua 10 ua 5 ua syncin/rt syncout clock generator /sync detector clk a=10 slope slope generator v sense1 v sense2 vin v out c in c out l in q h q l r s d bst c vcc c bst r fb 2 r fb 1 r t c res c ss r uv 2 r uv 1 r slope bst charge pump r comp c comp c hf 1.2 v 700 k 100 k mode skip cycle comparator 40 mv hysteresis 1.2 v diode emulation + - f clk / 2 or f clk r slope 6 u 10 v slope f sw 9 u = agnd -+ 20 mv + - vin + - opt diode emulation comparator v in copyright ? 2017, texas instruments incorporated
14 LM5122ZA snvsb54 ? may 2018 www.ti.com product folder links: LM5122ZA submit documentation feedback copyright ? 2018, texas instruments incorporated 7.3 feature description 7.3.1 undervoltage lockout (uvlo) the LM5122ZA features a dual level uvlo circuit. when the uvlo pin voltage is less than the 0.4-v uvlo standby enable threshold, the LM5122ZA is in the shutdown mode with all functions disabled. the shutdown comparator provides 0.1 v of hysteresis to avoid chatter during transition. if the uvlo pin voltage is greater than 0.4 v and below 1.2 v during power up, the controller is in standby mode with the vcc regulator operational and no switching at the ho and lo outputs. this feature allows the uvlo pin to be used as a remote shutdown function by pulling the uvlo pin down below the uvlo standby enable threshold with an external open collector or open drain device. figure 16. uvlo remote standby and shutdown control if the uvlo pin voltage is above the 1.2-v uvlo threshold and vcc voltage exceeds the vcc uv threshold, a start-up sequence begins. uvlo hysteresis is accomplished with an internal 10- a current source that is switched on or off into the impedance of the uvlo setpoint divider. when the uvlo pin voltage exceeds 1.2 v, the current source is enabled to quickly raise the voltage at the uvlo pin. when the uvlo pin voltage falls below the 1.2-v uvlo threshold, the current source is disabled causing the voltage at the uvlo pin to quickly fall. in addition to the uvlo hysteresis current source, a 5- s deglitch filter on both rising and falling edge of uvlo toggling helps preventing chatter upon power up or down. an external uvlo setpoint voltage divider from the supply voltage to agnd is used to set the minimum input operating voltage of the regulator. the divider must be designed such that the voltage at the uvlo pin is greater than 1.2 v when the input voltage is in the desired operating range. the maximum voltage rating of the uvlo pin is 15 v. if necessary, the uvlo pin can be clamped with an external zener diode. the uvlo pin should not be left floating. the values of r uv1 and r uv2 can be determined from equation 1 and equation 2 . (1) (2) where ? v hys is the desired uvlo hysteresis ? v in(startup) is the desired startup voltage of the regulator during turn-on. typical shutdown voltage during turn-off can be calculated as follows: (3) 7.3.2 high-voltage vcc regulator the LM5122ZA contains an internal high-voltage regulator that provides typical 7.6 v vcc bias supply for the controller and n-channel mosfet drivers. the input of vcc regulator, vin, can be connected to an input voltage source as high as 65 v. the vcc regulator turns on when the uvlo pin voltage is greater than 0.4 v. when the input voltage is below the vcc setpoint level, the vcc output tracks vin with a small dropout voltage. the output of the vcc regulator is current limited at 50 ma minimum. uv2 uv1 in(startup) 1.2v r r v 1.2v u a o ? ? : hys uv2 v r 10 $ : a o ? ? uvlo standby enable threshold shutdown uvlo threshold uvlo hysteresis current uvlo + - + - r uv2 r uv1 standby shutdown v in standby advance information in(shutdown) in(startup) hys v v v [v]
15 LM5122ZA www.ti.com snvsb54 ? may 2018 product folder links: LM5122ZA submit documentation feedback copyright ? 2018, texas instruments incorporated feature description (continued) upon power up, the vcc regulator sources current into the capacitor connected to the vcc pin. ti recommends a capacitance range for the vcc capacitor of 1 f to 47 f; capacitance at least 10 times greater than c bst value is also recommnded. when operating with a vin voltage less than 6 v, the value of vcc capacitor must be 4.7 f or greater. the internal power dissipation of the LM5122ZA device can be reduced by supplying vcc from an external supply. if an external vcc bias supply exists and the voltage is greater than 9 v and below 14.5 v. the external vcc bias supply can be applied to the vcc pin directly through a diode, as shown in figure 17 . figure 17. external bias supply when 9 v < v ext < 14.5 v a method to derive the vcc bias voltage with an additional winding on the boost inductor is shown in . this circuit must be designed to raise the vcc voltage above vcc regulation voltage to shut off the internal vcc regulator. figure 18. external bias supply using transformer the vcc regulator series pass transistor includes a diode between vcc and vin that must not be fully forward biased in normal operation, as shown in figure 19 . if the voltage of the external vcc bias supply is greater than the vin pin voltage, an external blocking diode is required from the input power supply to the vin pin to prevent the external bias supply from passing current to the input supply through vcc. the need for the blocking diode should be evaluated for all applications when the vcc is supplied by the external bias supply. especially, when the input power supply voltage is less than 4.5 v, the external vcc supply should be provided and the external blocking diode is required. + + + vcc 1 : n n u v in n u (v out -v in ) n u v out + + v in v out vcc c vcc external vcc supply advance information
16 LM5122ZA snvsb54 ? may 2018 www.ti.com product folder links: LM5122ZA submit documentation feedback copyright ? 2018, texas instruments incorporated feature description (continued) figure 19. vin configuration when v vin < v vcc 7.3.3 oscillator the LM5122ZA switching frequency is programmable by a single external resistor connected between the rt pin and the agnd pin. the resistor should be located very close to the device and connected directly to the rt pin and agnd pin. to set a desired switching frequency (f sw ), the resistor value can be calculated from equation 4 . (4) 7.3.4 slope compensation for duty cycles greater than 50%, peak-current-mode regulators are subject to sub-harmonic oscillation. sub- harmonic oscillation is normally characterized by observing alternating wide and narrow duty cycles. this sub- harmonic oscillation can be eliminated by a technique, which adds an artificial ramp, known as slope compensation, to the sensed inductor current. figure 20. slope compensation the amount of slope compensation is programmable by a single resistor connected between the slope pin and the agnd pin. the amount of slope compensation can be calculated as follows: where ? (5) in out v d' 1 v vin LM5122ZA v in vcc external vcc supply copyright ? 2017, texas instruments incorporated 9 t sw f 9 10 r u ? : a o ? advance information additional slope i lin u r s u 10 t on sensed inductor current = 9 slope sw slope 6 10 v = d' v f r u u a o ? ? u
17 LM5122ZA www.ti.com snvsb54 ? may 2018 product folder links: LM5122ZA submit documentation feedback copyright ? 2018, texas instruments incorporated feature description (continued) r slope value can be determined from equation 6 at minimum input voltage: where ? k = 0.82~1 as a default (6) from equation 6 , k can be calculated over the input range as follows: where ? (7) in any case, k should be greater than at least 0.5. at higher switching frequency over 500 khz, ti recommends that k factor be greater than or equal to 1 because the minimum on-time affects the amount of slope compensation due to internal delays. the sum of sensed inductor current and slope compensation should be less than comp output high voltage (v oh ) for proper startup with load and proper current limit operation. this limits the minimum value of r slope to be: ? this equation can be used in most cases ? consider this conservative selection when v in(min) < 5.5 v the slope pin cannot be left floating. 7.3.5 error amplifier the internal high-gain error amplifier generates an error signal proportional to the difference between the fb pin voltage and the internal precision 1.2-v reference. the output of the error amplifier is connected to the comp pin allowing the user to provide a type 2 loop compensation network. r comp , c comp and c hf configure the error amplifier gain and phase characteristics to achieve a stable voltage loop. this network creates a pole at dc, a mid-band zero (f z_ea ) for phase boost, and a high frequency pole (f p_ea ). the minimum recommended value of r comp is 2 k . see the feedback compensation section. (9) (10) z _ ea comp comp 1 f hz 2 r c a o ? ? s u u 9 slope sw 8 10 r f : u ! a o ? ? p_ea comp hf comp comp hf 1 f = hz c c 2 r c + c a o ? ? u s u u ? ? 1 9 in in s slope l 6 10 k = 1 + d' v r 10 r u u u ? ? u u u ? 1 9 in slope out in(min) s l 6 10 r k v v r 10 u u a o ? ? a o u u u ? : ? 9 in min slope sw out v 5.7 10 r 1.2 v f u ? ! u : a o ? ? ? ? 1 advance information in out v ' d v
18 LM5122ZA snvsb54 ? may 2018 www.ti.com product folder links: LM5122ZA submit documentation feedback copyright ? 2018, texas instruments incorporated feature description (continued) 7.3.6 pwm comparator the pwm comparator compares the sum of sensed inductor current and slope compensation ramp to the voltage at the comp pin through a 1.2-v internal comp to pwm voltage drop, and terminates the present cycle when the sum of sensed inductor current and slope compensation ramp is greater than v comp ? 1.2 v. figure 21. feedback configuration and pwm comparator 7.3.7 soft start the soft-start feature helps the regulator to gradually reach the steady state operating point, thus reducing start- up stresses and surges. the LM5122ZA regulates the fb pin to the ss pin voltage or the internal 1.2-v reference, whichever is lower. the internal 10- a soft-start current source gradually increases the voltage on an external soft-start capacitor connected to the ss pin. this results in a gradual rise of the output voltage starting from the input voltage level to the target output voltage. soft-start time (t ss ) which varies by the input supply voltage is calculated from equation 11 . (11) when the uvlo pin voltage is greater than the 1.2-v uvlo threshold and vcc voltage exceeds the vcc uv threshold, an internal 10- a soft-start current source turns on. at the beginning of this soft-start sequence, allow v ss to fall down below 25 mv using the internal ss pulldown switch. the ss pin can be pulled down by external switch to stop switching, but pulling up to enable switching is not allowed. the start-up delay (see figure 22 ) must be long enough for high-side boot capacitor to be fully charged up by internal bst charge pump. the value of c ss must be large enough to charge the output capacitor during soft-start time. (12) advance information ss in ss out c 1.2v v t 1 sec 10 $ 9 u u a o ? ? ? ? 1 out out ss out 10 $ 9 & c f 1.2 i u ! u a o ? ? v v out comp fb + - r fb2 r fb1 r comp c comp c hf ref error amplifier type 2 compensation components -+ pwm comparator + - (optional) 1.2 v + - cs amp a=10 r s slope generator r slope i lin csp csn
19 LM5122ZA www.ti.com snvsb54 ? may 2018 product folder links: LM5122ZA submit documentation feedback copyright ? 2018, texas instruments incorporated feature description (continued) figure 22. startup sequence 7.3.8 ho and lo drivers the LM5122ZA contains strong n-channel mosfet gate drivers and an associated high-side level shifter to drive the external n-channel mosfet switches. the high-side gate driver works in conjunction with an external boot diode d bst , and bootstrap capacitor c bst . during the on-time of the low-side n-channel mosfet driver, the sw pin voltage is approximately 0 v, and the c bst is charged from vcc through the d bst . ti recommends a 0.1- f or larger ceramic capacitor, connected with short traces between the bst and sw pin. the lo and ho outputs are controlled with an adaptive dead-time methodology which insures that both outputs are never enabled at the same time. when the controller commands lo to be enabled, the adaptive dead-time logic first disables ho and waits for ho-sw voltage to drop. lo is then enabled after a small delay (ho fall to lo rise delay). similarly, the ho turnon is delayed until the lo voltage has discharged. ho is then enabled after a small delay (lo fall to ho rise delay). this technique insures adequate dead-time for any size n-channel mosfet device, especially when vcc is supplied by a higher external voltage source. be careful when adding series gate resistors, as this may decrease the effective dead time. exercise care when selecting the n-channel mosfet devices threshold voltage, especially if the vin voltage range is below the vcc regulation level or a bypass operation is required. if the bypass operation is required, especially when output voltage is less than 12 v, select a logic level device for the high-side n-channel mosfet. during start-up at low input voltages, the low-side n-channel mosfet switch gate plateau voltage must be sufficient to completely enhance the n-channel mosfet device. if the low-side n-channel mosfet drive voltage is lower than the low-side n-channel mosfet device gate plateau voltage during startup, the regulator may not start up properly and it may stick at the maximum duty cycle in a high power dissipation state. this condition can be avoided by selecting a lower threshold n-channel mosfet switch or by increasing v in(startup) with the uvlo pin voltage programming. vcc uv threshold 0.4v 1.2v uvlo vout ss lo vcc 1.2v ho-sw shut down standby 10 a current source t ss startup delay v in advance information
20 LM5122ZA snvsb54 ? may 2018 www.ti.com product folder links: LM5122ZA submit documentation feedback copyright ? 2018, texas instruments incorporated feature description (continued) 7.3.9 bypass operation (v out = v in ) the LM5122ZA allows 100% duty cycle operation for the high-side synchronous switch when the input supply voltage is equal to or greater than the target output voltage. an internal 200 a bst charge pump maintains sufficient high-side driver supply voltage to keep the high-side n-channel mosfet switch on without the power stage switching. the internal bst charge pump is enabled when the uvlo pin voltage is greater than 1.2 v and the vcc voltage exceeds the vcc uv threshold. the bst charge pump generates 5.3-v minimum bst to sw voltage when sw voltage is greater than 9 v. this requires minimum 9 v boost output voltage for proper bypass operation. the leakage current of the boot diode should be always less than the bst charge pump sourcing current to maintain a sufficient driver supply voltage at both low and high temperatures. forced-pwm mode is the recommended pwm configuration when bypass operation is required. 7.3.10 cycle-by-cycle current limit the LM5122ZA features a peak cycle-by-cycle current limit function. if the csp to csn voltage exceeds the 75- mv cycle-by-cycle current-limit threshold, the current limit comparator immediately terminates the lo output. for the case where the inductor current may overshoot, such as inductor saturation, the current-limit comparator skips pulses until the current has decayed below the current-limit threshold. peak inductor current in current limit can be calculated as follows: (13) 7.3.11 clock synchronization the syncin/rt pin can be used to synchronize the internal oscillator to an external clock. a positive going synchronization clock at the rt pin must exceed the rt sync rising threshold and negative going synchronization clock at rt pin must exceed the rt sync falling threshold to trip the internal synchronization pulse detector. in master1 mode, two types of configurations are allowed for clock synchronization. with the configuration in figure 23 , the frequency of the external synchronization pulse is recommended to be within +40% and ? 20% of the internal oscillator frequency programmed by the rt resistor. for example, 900-khz external synchronization clock and 20-k ? rt resistor are required for 450-khz switching in master1 mode. the internal oscillator can be synchronized by ac coupling a positive edge into the rt pin. a 5-v amplitude pulse signal coupled through 100- pf capacitor is a good starting point. the rt resistor is always required with ac coupling capacitor with the figure 23 configuration, whether the oscillator is free running or externally synchronized. care should be taken to ensure that the rt pin voltage does not go below ? 0.3 v at the falling edge of the external pulse. this may limit the duty cycle of external synchronization pulse. there is approximately 400-ns delay from the rising edge of the external pulse to the rising edge of lo. figure 23. oscillator synchronization through ac coupling in master1 mode with the configuration in figure 24 , the internal oscillator can be synchronized by connecting the external synchronization clock into the rt pin through rt resistor with free of the duty cycle limit. the output stage of the external clock source should be a low impedance totem-pole structure. default logic state of f sync must be low. syncin/rt LM5122ZA r t f sync peak(cl) s 75mv i a r a o ? ? advance information
21 LM5122ZA www.ti.com snvsb54 ? may 2018 product folder links: LM5122ZA submit documentation feedback copyright ? 2018, texas instruments incorporated feature description (continued) figure 24. oscillator synchronization through a resistor in master1 mode in master2 and slave modes, connect this external synchronization clock directly to the rt pin and always provide continuously. the internal oscillator frequency can be either of two times faster than switching frequency or the same as the switching frequency by configuring the combination of fb and opt pins (see table 1 ). 7.3.12 maximum duty cycle when operating with a high pwm duty cycle, the low-side n-channel mosfet device is forced off each cycle. this forced lo off-time limits the maximum duty cycle of the controller. when designing a boost regulator with high switching frequency and high duty-cycle requirements, check the required maximum duty cycle. the minimum input supply voltage that can achieve the target output voltage is estimated from equation 14 or equation 15 . use equation 14 if v vcc is greater than 5.5 v or v vin is greater than 6 v. for low voltage applications that do not satisfy either of these conditions use equation 15 . (14) (15) in normal operation, about 100 ns of margin is recommended. 7.3.13 thermal protection internal thermal shutdown circuitry is provided to protect the controller in the event the maximum junction temperature is exceeded. when activated, typically at 165 c, the controller is forced into a low-power shutdown mode, disabling the output drivers, disconnection switch and the vcc regulator. this feature is designed to prevent overheating and destroying the device. 7.4 device functional modes 7.4.1 mode control (forced-pwm mode and diode-emulation mode) a fully synchronous boost regulator implemented with a high-side switch rather than a diode has the capability to sink current from the output in certain conditions such as light load, overvoltage, or load transient. the LM5122ZA can be configured to operate in either forced-pwm mode (fpwm) or diode emulation mode. in fpwm, reverse current flow in high-side n-channel mosfet switch is allowed, and the inductor current conducts continuously at light or no load conditions. the benefit of the fpwm mode is fast light load to heavy load transient response and constant frequency operation at light or no load conditions. to enable fpwm, connect the mode pin to vcc or tie to a voltage greater than 1.2 v. in fpwm, reverse current flow is not limited. in diode-emulation mode, current flow in the high-side switch is only permitted in one direction (source to drain). turnon of the high-side switch is allowed if csp to csn voltage is greater than 7 mv rising threshold of zero current detection during low-side switch on-time. if csp to csn voltage is less than 6-mv falling threshold of zero current detection during high-side switch on-time, reverse current flow from output to input through the high- side n-channel mosfet switch is prevented and discontinuous conduction mode of operation is enabled by latching off the high-side n-channel mosfet switch for the remainder of the pwm cycle. a benefit of the diode emulation is lower power loss at light load conditions. sw out in min v f v 400ns margin [v] u u syncin/rt LM5122ZA r t c sync advance information sw out in min v f v 750ns margin [v] u u
22 LM5122ZA snvsb54 ? may 2018 www.ti.com product folder links: LM5122ZA submit documentation feedback copyright ? 2018, texas instruments incorporated device functional modes (continued) figure 25. mode selection during start-up the LM5122ZA forces diode emulation, for start-up into a pre-biased load, while the ss pin voltage is less than 1.2 v. forced diode emulation is terminated by a pulse from the pwm comparator when ss is greater than 1.2 v. if there are no lo pulses during the soft-start period, a 350-ns one-shot lo pulse is forced at the end of soft start to help charge the boot strap capacitor. due to the internal current sense delay, configuring the LM5122ZA for diode emulation mode must be carefully evaluated if the inductor current ripple ratio is high and when operating at very high switching frequency. the transient performance during full load to no load in fpwm mode should also be verified. 7.4.2 mode control (skip-cycle mode and pulse-skipping mode) light load efficiency of the regulator typically drops as the losses associated with switching and bias currents of the converter become a significant percentage of the total power delivered to the load. in order to increase the light load efficiency the LM5122ZA provides two types of light load operation in diode-emulation mode. the skip-cycle mode integrated into the LM5122ZA controller reduces switching losses and improves efficiency at light-load condition by reducing the average switching frequency. skip-cycle operation is achieved by the skip cycle comparator. when a light-load condition occurs, the comp pin voltage naturally decreases, reducing the peak current delivered by the regulator. during comp voltage falling, the skip-cycle threshold is defined as v mode ? 20 mv and during comp voltage rising, it is defined as v mode + 20 mv. there is 40 mv of internal hysteresis in the skip cycle comparator. when the voltage at pwm comparator input falls below v mode ? 20 mv, both ho and lo outputs are disabled. the controller continues to skip switching cycles until the voltage at pwm comparator input increases to v mode + 20 mv, demanding more inductor current. the number of cycles skipped depends upon the load and the response time of the frequency compensation network. the internal hysteresis of skip-cycle comparator helps to produce a long skip cycle interval followed by a short burst of pulses. an internal 700-k pullup resistor and 100- k pulldown resistor sets the mode pin to 0.15 v as a default. because the peak current limit threshold is set to 750 mv, the default skip threshold corresponds to approximately 17% of the peak level. in practice the skip level is lower due to the added slope compensation. by adding an external pullup resistor to slope or vcc pin or adding an external pulldown resistor to the ground, the skip cycle threshold can be programmed. because the skip cycle comparator monitors the pwm comparator input which is proportional to the comp voltage, skip-cycle operation is not recommended when the bypass operation is required. conventional pulse-skipping operation can be achieved by connecting the mode pin to ground. the negative 20-mv offset at the positive input of skip-cycle comparator ensures the skip-cycle comparator does not trigger in normal operation. at light or no load conditions, the LM5122ZA skips lo pulses if the pulse width required by the regulator is less than the minimum lo on-time of the device. pulse skipping appears as a random behavior as the error amplifier struggles to find an average pulse width for lo in order to maintain regulation at light or no load conditions. skipcycle 1.2 v comp -+ 1.2v 700k 100k mode skip cycle comparator 1.2v diode emulation + - -+ 20mv default 150mv + - 40mv hysteresis advance information
23 LM5122ZA www.ti.com snvsb54 ? may 2018 product folder links: LM5122ZA submit documentation feedback copyright ? 2018, texas instruments incorporated device functional modes (continued) 7.4.3 hiccup-mode overload protection if cycle-by-cycle current limit is reached during any cycle, a 30- a current is sourced into the res capacitor for the remainder of the clock cycle. if the res capacitor voltage exceeds the 1.2-v restart threshold, a hiccup mode over load protection sequence is initiated; the ss capacitor is discharged to gnd, both lo and ho outputs are disabled, the voltage on the res capacitor is ramped up and down between 2-v hiccup counter lower threshold and 4-v hiccup counter upper threshold eight times by 10- a charge and 5- a discharge currents. after the eighth cycles, the ss capacitor is released and charged by the 10- a soft-start current again. if a 3-v zener diode is connected in parallel with the res capacitor, the regulator enters into the hiccup-mode off mode and then never restarts until uvlo shutdown is cycled. connect res pin directly to the agnd when the hiccup- mode operation is not used. figure 26. hiccup mode overload protection 7.4.4 slave mode and syncout the LM5122ZA is designed to easily implement dual (or higher) phase boost converters by configuring one controller as a master and all others as slaves. slave mode is activated by connecting the fb pin to the vcc pin. the fb pin is sampled during initial power-on and if a slave configuration is detected, the state is latched. in the slave mode, the error amplifier is disabled and has a high impedance output, 10- a hiccup-mode off-time charging current and 5- a hiccup-mode off-time discharging current are disabled, 5- a normal-state res discharging current and 10- a soft-start charging current are disabled, 30 a fault-state res charging current is changed to 35 a. 10- a uvlo hysteresis current source works the same as master mode. also, in slave mode, the internal oscillator is disabled, and an external synchronization clock is required. the syncout function provides a 180 phase shifted clock output, enabling easy dual-phase interleaved configuration. by directly connecting master1 syncout to slave1 syncin, the switching frequency of slave controller is synchronized to the master controller with 180 o phase shift. in master mode, if opt pin is tied to gnd, an internal oscillator clock divided by two with 50% duty cycle is provided to achieve an 180 o phase-shifted operation in two phase interleaved configuration. switching frequency of master controller is half of the external clock frequency with this configuration. if the opt pin voltage is higher than 2.7-v opt threshold or the pin is tied to vcc, syncout is disabled and the switching frequency of master controller becomes the same as the external clock frequency. an external synchronization clock should be always provided and directly connected to syncin for master2, slave1 and slave2 configurations. see interleaved boost configuration for detailed information. table 1. LM5122ZA multiphase configuration multiphase configuration fb opt error amplifier switching frequency syncout master1 feedback gnd enable f sync /2, free running with rt resistor f sync /2, f sw ? 180 o slave1 vcc gnd disable f sync, no free running disable master2 feedback vcc enable f sync, no free running disable slave2 vcc vcc disable f sync /2, no free running f sync /2, f sw ? 180 o 4v 2.0v 1.2v count to eight restart delay res ss hiccup mode off-time i res = 30 a i res = 10 a i res = -5 a lo ho t rd t res advance information
24 LM5122ZA snvsb54 ? may 2018 www.ti.com product folder links: LM5122ZA submit documentation feedback copyright ? 2018, texas instruments incorporated 8 application and implementation note information in the following applications sections is not part of the ti component specification, and ti does not warrant its accuracy or completeness. ti ? s customers are responsible for determining suitability of components for their purposes. customers should validate and test their design implementation to confirm system functionality. 8.1 application information the LM5122ZA device is a step-up dc/dc converter. the device is typically used to convert a lower dc voltage to a higher dc voltage. use the following design procedure to select component values for the LM5122ZA device. alternately, use the webench ? software to generate a complete design. the webench software uses an iterative design procedure and accesses a comprehensive database of components when generating a design. this section presents a simplified discussion of the design process. 8.1.1 feedback compensation the open loop response of a boost regulator is defined as the product of modulator transfer function and feedback transfer function. when plotted on a db scale, the open loop gain is shown as the sum of modulator gain and feedback gain. the modulator transfer function of a current mode boost regulator including a power stage transfer function with an embedded current loop can be simplified as one pole, one zero, and one right- half-plane (rhp) zero system. modulator transfer function is defined as follows: where ? ? ? ? ? ? n is the number of the phase. (16) if the equivalent series resistance (esr) of c out (r esr ) is small enough and the rhp zero frequency is far away from the target crossover frequency, the modulator transfer function can be further simplified to one pole system, and the voltage loop can be closed with only two loop compensation components, r comp and c comp , leaving a single pole response at the crossover frequency. a single pole response at the crossover frequency yields a very stable loop with 90 degrees of phase margin. the feedback transfer function includes the feedback resistor divider and loop compensation of the error amplifier. r comp , c comp , and optional c hf configure the error amplifier gain and phase characteristics, create a pole at origin, a low frequency zero and a high frequency pole. feedback transfer function is defined as follows: z _ esr z _ rhp out m comp p _ lf s s 1 1 ? & & v (s) a ? v (s) s 1 & u ? ? ? ? ? 1 ? 1 u ? ? ? 1 p _ lf ou o t l ad & /rdg sroh r c 2 u ' load m s _ eq s r d a (modulator dc gain) r a 2 u u z _ esr esr out 1 & (65]hur r c u advance information 2 load z _ rhp in _ eq ' r (d ) & 5+3]hur l u s in in _ eq s _ eq r l l , r n n
25 LM5122ZA www.ti.com snvsb54 ? may 2018 product folder links: LM5122ZA submit documentation feedback copyright ? 2018, texas instruments incorporated application information (continued) where ? ? ? (17) the pole at the origin minimizes the output steady state error. place the low frequency zero to cancel the load pole of the modulator. the high frequency pole can be used to cancel the zero created by the output capacitor esr or to decrease noise susceptibility of the error amplifier. by placing the low frequency zero an order of magnitude less than the crossover frequency, the maximum amount of phase boost can be achieved at the crossover frequency. the high frequency pole should be placed beyond the crossover frequency since the addition of c hf adds a pole in the feedback transfer function. the crossover frequency (open loop bandwidth) is usually selected between one twentieth and one fifth of the f sw . in a simplified formula, the estimated crossover frequency can be defined as: where ? (18) for higher crossover frequency, r comp can be increased, while proportionally decreasing c comp . conversely, decreasing r comp while proportionally increasing c comp , results in lower bandwidth while keeping the same zero frequency in the feedback transfer function. the modulator transfer function can be measured by a network analyzer and the feedback transfer function can be configured for the desired open loop transfer function. if the network analyzer is not available, step load transient tests can be performed to verify acceptable performance. the step load goal is minimum overshoot/undershoot with a damped response. 8.1.2 sub-harmonic oscillation peak current mode regulator can exhibit unstable behavior when operating above 50% duty cycle. this behavior is known as sub-harmonic oscillation and is characterized by alternating wide and narrow pulses at the sw pin. sub-harmonic oscillation can be prevented by adding an additional slope voltage ramp (slope compensation) on top of the sensed inductor current. by choosing k 0.82~1, the sub-harmonic oscillation is eliminated even with wide varying input voltage. in time-domain analysis, the steady-state inductor current starting from an initial point returns to the same point. when the amplitude of an end cycle current error (di 1 ) caused by an initial perturbation (di 0 ) is less than the amplitude of di 0 or di 1 /di 0 > ? 1, the perturbation naturally disappears after a few cycles. when dl 1 /dl 0 < ? 1, the initial perturbation no longer disappear, it results in sub-harmonic oscillation in steady-state. fb fb2 comp hf 1 a (feedback dc gain) r c c u z _ ea comp fb out p _ ea 1 ? & v a ? v s s 1 & s u u ? ? ? 1 p _ ea comp hf 1 & +ljkiuhtxhqf\sroh r c u z _ ea comp comp 1 & /rziuhtxhqf\]hur r c u comp cross s _ eq fb2 s out r f d' [hz] r r a c u s u u u u advance information in out v ' d v
26 LM5122ZA snvsb54 ? may 2018 www.ti.com product folder links: LM5122ZA submit documentation feedback copyright ? 2018, texas instruments incorporated application information (continued) figure 27. effect of initial perturbation when dl 1 /dl 0 < ? 1 di 1 /di 0 can be calculated as: (19) the relationship between di 1 /di 0 and k factor is illustrated graphically in figure 28 . figure 28. dl 1 /dl 0 vs k factor the absolute minimum value of k is 0.5. when k < 0.5, the amplitude of dl 1 is greater than the amplitude of dl 0 and any initial perturbation results in sub-harmonic oscillation. if k = 1, any initial perturbation is removed in one switching cycle. this is known as one-cycle damping. when ? 1 < dl 1 /dl 0 < 0, any initial perturbationis under- damped. any perturbation is over-damped when 0 < dl 1 /dl 0 < 1. in the frequency-domain, q, the quality factor of sampling gain term in modulator transfer function, is used to predict the tendency for sub-harmonic oscillation, which is defined as: (20) the relationship between q and k factor is shown in figure 29 . 1 q k 0.5 s 1 0 di 1 1 di k advance information steady-state inductor current di 0 di 1 t on inductor current with initial perturbation
27 LM5122ZA www.ti.com snvsb54 ? may 2018 product folder links: LM5122ZA submit documentation feedback copyright ? 2018, texas instruments incorporated application information (continued) (1) comprehensive equation includes an inductor pole and a gain peaking at f sw / 2, which is caused by sampling effect of the current mode control. also, it assumes that a ceramic capacitor c out2 (no esr) is connected in parallel with c out1 . r esr1 represents esr of c out1 . (2) with multiphase configuration, , , , and c out = c out of each phase x n, where n = number of phases. as is the current sense amplifier gain. figure 29. sampling gain q vs k factor the recommended absolute minimum value of k is 0.5. high gain peaking when k is less than 0.5 results sub- harmonic oscillation at f sw /2. a higher value of k factor may introduce additional phase shift near the crossover frequency, but has the benefit of reducing noise susceptibility in current loop. the maximum allowable value of k factor can be calculated by the maximum crossover frequency equation in frequency analysis formulas in table 2 . table 2. boost regulator frequency analysis simplified formula comprehensive formula (1) modulator transer function modulator dc gain (2) rhp zero (2) esr zero esr pole not considered dominant load pole sampled gain inductor pole not considered or quality factor not considered advance information p _ esr esr1 out1 out2 1 & r c / /c u z _ esr esr1 out1 1 & r c u z _ esr esr out 1 & r c u load m s _ eq s r d' a r a 2 u u out load out v r i of each phase n u s s _ eq r r n 2 load z _ rhp in _ eq r (d') & l u esr rhp z z out m 2 comp 2 p_lf p _ esr p_hf n s s 1 1 ? & & v s a ? v s s s s s 1 1 1 & & & & ? ? u ? ? ? 1 ? 1 u u u ? ? ? ? ? ? ? 1 ? 1 ? 1 in in _ eq l l n out m co z _ esr z _ rhp p f mp _ l s s 1 1 s 1 ? v (s) a ? v (s) u ? ? ? ? z z ? 1 ? 1 u ? z ? 1 ? p _ lf load out 2 & r c u sw p _ hf & k f 0.5 p _ hf n & 4 & u 1 q k 0.5 s
28 LM5122ZA snvsb54 ? may 2018 www.ti.com product folder links: LM5122ZA submit documentation feedback copyright ? 2018, texas instruments incorporated application information (continued) table 2. boost regulator frequency analysis (continued) simplified formula comprehensive formula (1) (3) assuming , , , , and . (4) the frequency at which 45 phase shift occurs in modulator phase characteristics. sub-harmonic double pole not considered or k factor k = 1 feedback transfer function feedback dc gain mid-band gain low frequency zero high frequency pole open loop response crossover frequency (3) (open loop band width) use graphic tool maximum cross over frequency (4) or , whichever is smaller advance information z _ rhp & 2 4 u s u in out v d' v load out comp comp r c c 4 r u u z _ rhp cross & f 2 10 u s u z _ ea comp comp 1 & r c u comp p chf _ e c mp a o r c / /c 1 & u fb fb2 comp hf 1 a r (c c ) u comp fb _ mid fb2 r a r 9 ' in in s slope l 6 10 k 1 d v r 10 r u u u ? ? u u u ? 1 z _ ea comp fb out p _ ea s 1 ? & v (s) a ? v (s) s s 1 & u u ? ? ? 1 sw n sw & & i 2 s u p _ ea comp hf 1 & r c u sw n f 2 f hf z _ esr z _ rhp z _ ea m fb 2 2 p _ ea p _ lf p _ esr p n s s s 1 1 1 & & & t a a s s s s s s 1 1 1 1 & & & & & u ? ? ? ? ? 1 ? 1 u u u u ? ? u u ? ? ? ? ? ? ? 1 ? 1 ? 1 ? 1 s z _ ea p _ lf & & z _ esr z _ rhp z _ ea m fb p _ lf p _ ea s s s 1 1 1 & & & t a a s s 1 s 1 & & u ? ? ? ? ? 1 ? 1 u u u u ? ? ? ? ? 1 ? 1 s ' comp cross s _ eq fb2 s out r f d r r a c u s u u u u 2 sw cross _max f 1 4 q 1 4 q f u u ? ? 1 u p _ ea z _ esr & & z _rhp sw cross _max & f or whichever is smaller 5 2 4 f u s u
29 LM5122ZA www.ti.com snvsb54 ? may 2018 product folder links: LM5122ZA submit documentation feedback copyright ? 2018, texas instruments incorporated 8.1.3 interleaved boost configuration interleaved operation offers many advantages in single output, high current applications such as higher efficiency, lower component stresses and reduced input and output ripple. for dual phase interleaved operation, the output power path is split reducing the input current in each phase by one-half. ripple currents in the input and output capacitors are reduced significantly since each channel operates 180 degrees out of phase from the other. shown in figure 30 is a normalized (i rms / i out ) output capacitor ripple current vs duty cycle for both a single phase and dual phase boost converter, where i rms is the output current ripple rms. figure 30. normalized output capacitor rms ripple current to configure for dual phase interleaved operation, configure one device as a master and configure the other device in slave mode by connecting fb to vcc. also connect comp, uvlo, res, ss and syncout on the master side to comp, uvlo, res, ss and syncin on slave side, respectively. the compensation network is connected between master fb and the common comp connection. the output capacitors of the two power stages are connected together at the common output. figure 31. dual phase interleaved boost configuration advance information master vcc csn syncin/rt res ss uvlo vin syncout bst slope comp fb ho lo sw + v out vcc csn syncin/rt res ss uvlo vin bst slope comp fb ho lo sw vcc slave v supply csp csp opt opt v supply
30 LM5122ZA snvsb54 ? may 2018 www.ti.com product folder links: LM5122ZA submit documentation feedback copyright ? 2018, texas instruments incorporated shown in figure 32 is a dual phase timing diagram. the 180 phase shift is realized by connecting syncout on the master side to the syncin on the slave side. figure 32. dual phase configuration and timing diagram each channel is synchronized by an individual external clock in figure 33 . the syncout pin is used in figure 34 requiring only one external clock source. a 50% duty cycle of external synchronization pulse should be always provided with this daisy chain configuration. current sharing between phases is achieved by sharing one error amplifier output of the master controller with the 3 slave controllers. resistor sensing is a preferred method of current sensing to accurately balance the phase currents. figure 33. 4-phase timing diagram individual clock syncin(master) internal clk(master) sw(master) syncout(master) syncin(slave) (50%duty-cycle) internal clk(slave) sw(slave) f sync gnd syncin/rt master syncin/rt slave optional f sync (5v pp ) r t duty cycle of f sync should be controlled for rt not to go below gnd c sync free running when no external synchronization. opt=gnd opt=gnd syncout advance information syncin/rt master syncin/rt slave1 syncin/rt slave3 syncin/rt slave2 f sync should be always provided (5v pp ) opt=gnd opt=gnd opt=gnd syncin_master syncin_slave2 syncin_slave1 syncin_slave3 opt=vcc f sync1 f sync2 f sync3 f sync4 f sync1 f sync2 f sync3 f sync4
31 LM5122ZA www.ti.com snvsb54 ? may 2018 product folder links: LM5122ZA submit documentation feedback copyright ? 2018, texas instruments incorporated figure 34. 4-phase timing diagram daisy chain 8.1.4 dcr sensing for the applications requiring lowest cost with minimum conduction loss, inductor dc resistance (dcr) is used to sense the inductor current rather than using a sense resistor. shown in figure 35 is a dcr sensing configuration using two dcr sensing resistors and one capacitor. figure 35. dcr sensing r csn and c dcr selection must meet equation 21 because this indirect current sensing method requires a time constant matching. c dcr is usually selected to be in the range of 0.1 f to 2.2 f. (21) smaller value of r csn minimizes the voltage drop caused by csn bias current, but increases the dynamic power dissipation of r csn . the dc voltage drop of r csn can be compensated by selecting the same value of r csp , but the gain of current amplifier, which is typically 10, is affected by adding r csp . the gain of current amplifier with the dcr sensing network can be determined as: (22) due to the reduced accuracy of dcr sensing, ti recommends fpwm operation when dcr sensing is used. d q qz syncin master syncin slave1 syncin slave3 syncin slave2 f sync should be always provided (5vpp) f sync opt=vcc f sync syncin_master syncin_slave2 opt=gnd opt=gnd opt=gnd syncin_slave1 syncin_slave3 r t r t syncout syncout + v in LM5122ZA csn csp sw + v out ho lo l in r dcr r csp r csn c dcr copyright ? 2017, texas instruments incorporated in dcr csn dcr l c r r u advance information cs _ dcr csp a 12.5 k / (1.25 k r ) : :
32 LM5122ZA snvsb54 ? may 2018 www.ti.com product folder links: LM5122ZA submit documentation feedback copyright ? 2018, texas instruments incorporated 8.1.5 output overvoltage protection output overvoltage protection can be achieved by adding a simple external circuit. the output overvoltage protection circuit shown in figure 36 shuts down the LM5122ZA when the output voltage exceeds the overvoltage threshold set by the zener diode. figure 36. output overvoltage protection 8.1.6 sepic converter simplified schematic figure 37. sepic converter simplified schematic advance information v out LM5122ZA uvlo vcc LM5122ZA csp syncin/rt res ss uvlo vin syncout agnd bst mode pgnd slope comp fb ho lo sw opt v out csn + v supply coupled inductor 9v ~ 36v 12v copyright ? 2017, texas instruments incorporated
33 LM5122ZA www.ti.com snvsb54 ? may 2018 product folder links: LM5122ZA submit documentation feedback copyright ? 2018, texas instruments incorporated 8.1.7 non-isolated synchronous flyback converter simplified schematic figure 38. non-isolated synchronous flyback converter simplified schematic 8.1.8 negative to positive conversion figure 39. negative to positive converter simplified schematic advance information vcc LM5122ZA csp syncin/rt res ss uvlo vin syncout agnd bst mode pgnd slope comp fb ho lo sw opt v out csn + v supply coupled inductor 9v ~ 36v 12v 744851101 copyright ? 2017, texas instruments incorporated vcc LM5122ZA csp syncin/rt res ss uvlo vin syncout agnd bst mode pgnd slope comp fb ho lo sw opt +v out csn -v in -v in -v in -v in load -v in -v in -v in -v in + copyright ? 2017, texas instruments incorporated
34 LM5122ZA snvsb54 ? may 2018 www.ti.com product folder links: LM5122ZA submit documentation feedback copyright ? 2018, texas instruments incorporated 8.2 typical application figure 40. single phase example schematic advance information LM5122ZAmh
35 LM5122ZA www.ti.com snvsb54 ? may 2018 product folder links: LM5122ZA submit documentation feedback copyright ? 2018, texas instruments incorporated typical application (continued) 8.2.1 design requirements design parameters value output voltage (v out ) 24 v full load current (i out ) 4.5 a output power 108 w minimum input voltage (v in(min) ) 9 v typical input voltage (v in(typ) ) 12 v maximum input voltage (v in(max) ) 20 v switching frequency (f sw ) 250 khz 8.2.2 detailed design procedure 8.2.2.1 timing resistor r t generally, higher frequency applications are smaller but have higher losses. operation at 250 khz is selected for this example as a reasonable compromise between small size and high-efficiency. the value of r t for 250 khz switching frequency is calculated as follows: (23) a standard value of 36.5 k ? is chosen for r t . 8.2.2.2 uvlo divider r uv2 , r uv1 the desired start-up voltage and the hysteresis are set by the voltage divider r uv2 , r uv1 . the uvlo shutdown voltage should be high enough to enhance the low-side n-channel mosfet switch fully. for this design, the startup voltage is set to 8.7 v which is 0.3 v below v in(min) . v hys is set to 0.5 v. this results 8.2 v of v in(shutdown) . the values of r uv2 , r uv1 are calculated as follows: (24) (25) a standard value of 49.9 k ? is selected for r uv2 . r uv1 is selected to be a standard value of 8.06 k ? . 8.2.2.3 input inductor l in the inductor ripple current is typically set between 20% and 40% of the full load current, known as a good compromise between core loss and copper loss of the inductor. higher ripple current allows for a smaller inductor size, but places more of a burden on the output capacitor to smooth the ripple voltage on the output. for this example, a ripple ratio (rr) of 0.25, 25% of the input current was chosen. knowing the switching frequency and the typical output voltage, the inductor value can be calculated as follows: (26) the closest standard value of 10 h was chosen for l in . the saturation current rating of inductor should be greater than the peak inductor current, which is calculated at the minimum input voltage and full load. 8.7 v startup voltage is used conservatively. (27) advance information uv2 uv1 in(startup) 1.2v r 1.2v 50 k r 8 k v 1.2v 8.7v 1.2v u u : : hys uv2 hys v 0.5 v r 50 k i 10 a : p 9 9 t sw 9 10 9 10 r 36.0 k 25 f 0 khz u u : in in peak in in sw out v v 1 24v 4.5a 1 8.7v 8.7v i i 1 1 13.5 a 2 l f v 8.7v 2 10 + n+] 9 u u u u u ? ? u u ? 1 ? 1 in in in in sw out v v 1 12v 1 12v l 1 1 10.7 + 108w i rr v 250 khz 24v 0. f 25 12v u u u u ? ? u ? 1 ? 1 u
36 LM5122ZA snvsb54 ? may 2018 www.ti.com product folder links: LM5122ZA submit documentation feedback copyright ? 2018, texas instruments incorporated 8.2.2.4 current sense resistor r s the maximum peak input current capability should be 20% to 50% higher than the required peak current at low input voltage and full load, accounting for tolerances. for this example, 40% margin is chosen. (28) a closest standard value of 4 m ? is selected for r s . the maximum power loss of r s is calculated as follows. (29) 8.2.2.5 current sense filter r csfp , r csfn , c cs the current sense filter is optional. 100 pf of c cs and 100 ? of r csfp , r csfn are normal recommendations. because csp and csn pins are high impedance, place c cs physically as close to the device. figure 41. current sense filter 8.2.2.6 slope compensation resistor r slope the k value is selected to be 1 at the minimum input voltage. carefully select r slope so that the sum of sensed inductor current and slope compensation is less than comp output high voltage. (30) (31) a closest standard value of 100 k ? is selected for r slope . 8.2.2.7 output capacitor c out the output capacitors smooth the output voltage ripple and provide a source of charge during transient loading conditions. also the output capacitors reduce the output voltage overshoot when the load is disconnected suddenly. ripple current rating of output capacitor should be carefully selected. in boost regulator, the output is supplied by discontinuous current and the ripple current requirement is usually high. in practice, the ripple current requirement can be dramatically reduced by placing high-quality ceramic capacitors earlier than the bulk aluminum capacitors close to the power switches. the output voltage ripple is dominated by esr of the output capacitors. paralleling output capacitor is a good choice to minimize effective esr and split the output ripple current into capacitors. in this example, three 330 f aluminum capacitors are used to share the output ripple current and source the required charge. the maximum output ripple current can be simply calculated at the minimum input voltage as follows: 9 9 slope sw 8 10 8 10 r 32 k 250 khz f u u ! : + v in LM5122ZA csn csp r csfn c cs r s r csfp copyright ? 2017, texas instruments incorporated 2 2 loss(rs) p i r (13.5 a 1.4) 4 m 1.43 w u u : cs th1 s peak(cl) v 75 mv r 3.97 m i 13.5 a 1.4 : u advance information 9 9 in slope out in(min) s l 6 10 10 + r 100 k 1 24v 9v 4m 10 k v v r 10 u u u u : u u : u a o u u u ? ?
37 LM5122ZA www.ti.com snvsb54 ? may 2018 product folder links: LM5122ZA submit documentation feedback copyright ? 2018, texas instruments incorporated (32) assuming 60 m ? of esr per an output capacitor, the output voltage ripple at the minimum input voltage is calculated as follows: (33) in practice, four 10- f ceramic capacitors are additionally placed earlier than the bulk aluminum capacitors to reduce the output voltage ripple and split the output ripple current. due to the inherent path from input to output, unlimited inrush current can flow when the input voltage rises quickly and charges the output capacitor. the slew rate of input voltage rising should be controlled by a hot-swap or by starting the input power supply softly for the inrush current not to damage the inductor, sense resistor or high-side n-channel mosfet switch. 8.2.2.8 input capacitor c in the input capacitors smooth the input voltage ripple. assuming high-quality ceramic capacitors are used for the input capacitors, the maximum input voltage ripple which happens when the input voltage is half of the output voltage can be calculated as follows: (34) the value of input capacitor is also a function of source impedance, the impedance of source power supply. the more input capacitor will be required to prevent a chatter condition upon power up if the impedance of source power supply is not enough low. 8.2.2.9 vin filter r vin , c vin an r-c filter (r vin , c vin ) on vin pin is optional. it is not required if c in capacitors are high-quality ceramic capacitors and placed physically close to the device. the filter helps to prevent faults caused by high frequency switching noise injection into the vin pin. a 0.47- f ceramic capacitor is used this example. 3 of r vin and 0.47 f of c vin are normal recommendations. ti recommends a larger filter with 2.2 f to 4.7 f c vin when the input voltage is lower than 8 v or the required duty cycle is close to the maximum duty-cycle limit. figure 42. vin filter 8.2.2.10 bootstrap capacitor c bst and boost diode d bst the bootstrap capacitor between the bst and sw pin supplies the gate current to charge the high-side n- channel mosfet device gate during each cycle ? s turnon and also supplies recovery charge for the bootstrap diode. these current peaks can be several amperes. the recommended value of the bootstrap capacitor is 0.1 f. c bst must be a good-quality, low-esr, ceramic capacitor located at the pins of the device to minimize potentially damaging voltage transients caused by trace inductance. the minimum value for the bootstrap capacitor is calculated as follows: where advance information out ripple _ max(cout) esr in(min) out sw out i 1 4.5a 60m 1 v r 0.252v v 9v 4 c f 3 4 3 330 ) n+] 24v v : u u ? ? u u u u u ? 1 ? 1 out ripple _ max(cout) in(min) out i 4.5a i 6a v 9v 2 2 24v v u u v in LM5122ZA vin r vin c vin 2 out ripple _ max(cin) 2 in in sw v 24v v 0.09 32 l c f 32 10 + ) n+] u u u u u u u v g bst bst q c f ? 9 a o ? ?
38 LM5122ZA snvsb54 ? may 2018 www.ti.com product folder links: LM5122ZA submit documentation feedback copyright ? 2018, texas instruments incorporated ? q g is the high-side n-channel mosfet gate charge ? v bst is the tolerable voltage droop on c bst , which is typically less than 5% of vcc or 0.15 v, conservatively (35) in this example, the value of the bst capacitor (c bst ) is 0.1 f. the voltage rating of d bst must be greater than the peak sw node voltage plus 16 v. a low leakage diode is mandatory for the bypass operation. the leakage current of d bst must be low enough for the bst charge pump to maintain a sufficient high-side driver supply voltage at high temperature. a low leakage diode also prevents the possibility of excessive vcc voltage during shutdown, in high output voltage applications. if the leakage is excessive, a zener vcc clamp or bleed resistor may be required. high-side driver supply voltage must be greater than the high-side n-channel mosfet switch ? s gate plateau at the minimum input voltage. 8.2.2.11 vcc capacitor c vcc the primary purpose of the vcc capacitor is to supply the peak transient currents of the lo driver and bootstrap diode as well as provide stability for the vcc regulator. these peak currents can be several amperes. the value of c vcc must be at least 10 times greater than the value of c bst and should be a good-quality, low-esr, ceramic capacitor. place c vcc close to the pins of the device to minimize potentially damaging voltage transients caused by trace inductance. a value of 4.7 f was selected for this design example. 8.2.2.12 output voltage divider r fb1 , r fb2 r fb1 and r fb2 set the output voltage level. the ratio of these resistors is calculated as follows: (36) the ratio between r comp and r fb2 determines the mid-band gain, a fb_mid . a larger value for r fb2 may require a corresponding larger value for r comp . r fb2 should be large enough to keep the total divider power dissipation small. 49.9 k in series with 825 was chosen for high-side feedback resistors in this example, which results in a r fb1 value of 2.67 k for 24-v output. 8.2.2.13 soft-start capacitor c ss the soft-start time (t ss ) is the time for the output voltage to reach the target voltage from the input voltage. the soft-start time is not only proportional with the soft-start capacitor, but also depends on the input voltage. with 0.1 f of c ss , the soft-start time is calculated as follows: (37) (38) 8.2.2.14 restart capacitor c res the restart capacitor determines restart delay time t rd and hiccup mode off time t res (see figure 26 ). t rd must be greater than t ss(max) . the minimum required value of c res can be calculated at the low input voltage as follows: (39) a standard value of 0.47 f is selected for c res . 8.2.2.15 low-side power switch q l selection of the power n-channel mosfet devices by breaking down the losses is one way to compare the relative efficiencies of different devices. losses in the low-side n-channel mosfet device can be separated into conduction loss and switching loss. low-side conduction loss is approximately calculated as follows: in(max) ss ss(min) ss out v c 1.2v 0.1 ) 9 9 t 1 1 2 msec i v 10 $ 9 u u u u ? ? ? ? 1 ? 1 out fb2 fb1 v r 1 r 1.2v res ss(max) res(min) res i t 30 $ pvhf c 0.19 f v 1.2v u u p in(min) ss ss(max) ss out v c 1.2v 0.1 ) 9 9 t 1 1 7.5 msec i v 10 $ 9 u u u u ? ? ? ? 1 ? 1 advance information
39 LM5122ZA www.ti.com snvsb54 ? may 2018 product folder links: LM5122ZA submit documentation feedback copyright ? 2018, texas instruments incorporated where ? d is the duty cycle ? the factor of 1.3 accounts for the increase in the n-channel mosfet device on-resistance due to heating (40) alternatively, the factor of 1.3 can be eliminated, and the high temperature on-resistance of the n-channel mosfet device can be estimated using the r ds(on) vs temperature curves in the n-channel mosfet datasheet. switching loss occurs during the brief transition period as the low-side n-channel mosfet device turns on and off. during the transition period both current and voltage are present in the channel of the n-channel mosfet device. the low-side switching loss is approximately calculated as follows: (41) t r and t f are the rise and fall times of the low-side n-channel mosfet device. the rise and fall times are usually mentioned in the n-channel mosfet data sheet or can be empirically observed with an oscilloscope. an additional schottky diode can be placed in parallel with the low-side n-channel mosfet switch, with short connections to the source and drain in order to minimize negative voltage spikes at the sw node. sw(ls) out in r f sw p 0.5 v i (t t ) f [w] u u u u advance information 2 2 out out in cond(ls) ds _ on(ls) ds _ on(ls) in out in i v v p d i r 1.3 1 r 1.3 [w] v v u u u u u u u ? ? ? 1 ? 1
40 LM5122ZA snvsb54 ? may 2018 www.ti.com product folder links: LM5122ZA submit documentation feedback copyright ? 2018, texas instruments incorporated 8.2.2.16 high-side power switch q h and additional parallel schottky diode losses in the high-side n-channel mosfet device can be separated into conduction loss, dead-time loss, and reverse recovery loss. switching loss is calculated for the low-side n-channel mosfet device only. switching loss in the high-side n-channel mosfet device is negligible because the body diode of the high-side n-channel mosfet device turns on before and after the high-side n-channel mosfet device switches. high-side conduction loss is approximately calculated as follows: (42) dead-time loss is approximately calculated as follows: where ? v d is the forward voltage drop of the high-side nmos body diode. (43) reverse recovery characteristics of the high-side n-channel mosfet switch strongly affect efficiency, especially when the output voltage is high. small reverse recovery charge helps to increase the efficiency while also minimizes switching noise. reverse recovery loss is approximately calculated as follows: (44) where ? q rr is the reverse recovery charge of the high-side n-channel mosfet body diode. (45) an additional schottky diode can be placed in parallel with the high-side switch to improve efficiency. usually, the power rating of this parallel schottky diode can be less than the high-side switch ? s because the diode conducts only during dead-times. the power rating of the parallel diode should be equivalent or higher than high-side switch ? s if bypass operation is required, hiccup mode operation is required or any load exists before switching. 8.2.2.17 snubber components a resistor-capacitor snubber network across the high-side n-channel mosfet device reduces ringing and spikes at the switching node. excessive ringing and spikes can cause erratic operation and can couple noise to the output voltage. selecting the values for the snubber is best accomplished through empirical methods. first, make sure the lead lengths for the snubber connections are very short. start with a resistor value between 5 and 50 . increasing the value of the snubber capacitor results more damping, but this also results higher snubber losses. select a minimum value for the snubber capacitor that provides adequate damping of the spikes on the switch waveform at heavy load. a snubber may not be necessary with an optimized layout. rr(hs) out rr sw p v q f [w] u u advance information dt(hs) d in dlh dhl sw p v x i x (t t ) x f [w] 2 2 out out in cond(hs) ds _ on(hs) ds _ on(hs) in out in i v v p (1 d) i r 1.3 r 1.3 [w] v v u u u u u u u ? ? ? 1 ? 1
41 LM5122ZA www.ti.com snvsb54 ? may 2018 product folder links: LM5122ZA submit documentation feedback copyright ? 2018, texas instruments incorporated 8.2.2.18 loop compensation components c comp , r comp , c hf r comp , c comp and c hf configure the error amplifier gain and phase characteristics to produce a stable voltage loop. for a quick start, follow the following 4 steps: 1. select f cross select the cross over frequency (f cross ) at one fourth of the rhp zero or one tenth of the switching frequency whichever is lower. (46) (47) 5.3 khz of the crossover frequency is selected between two. rhp zero at minimum input voltage should be considered if the input voltage range is wide. 2. determine required r comp knowing f cross , r comp is calculated as follows: (48) a standard value of 68.1 k ? is selected for r comp 3. determine c comp to cancel load pole. place error amplifier zero at the twice of load pole frequency. knowing r comp , c comp is calculated as follows: (49) a standard value of 22 nf is selected for c comp 4. determine c hf to cancel esr zero. knowing r comp , r esr and c comp , c hf is calculated as follows: (50) a standard value of 330 pf is selected for c hf . sw 25 z f kh 10 advance information esr out hf com comp comp esr ou p t c c r r c c 3 7 pf c 0 r u u u u load out comp comp r x c c 20.2nf 4 x r out comp cross s fb2 out in v r f r r 10 c 68.5 k v u s u u u u u : 2 out in 2 z _ rhp load out out in _ eq in _ eq v v ( ) f r (d') i v 5.3 khz 4 4 2 l 4 2 l u u u s u u s u
42 LM5122ZA snvsb54 ? may 2018 www.ti.com product folder links: LM5122ZA submit documentation feedback copyright ? 2018, texas instruments incorporated 8.2.3 application curves c1: f sync c2: sw v supply = 12 v, f sync = 500 khz figure 43. clock synchronization c1:sw v supply = 12 v i load = 0 a figure 44. forced pwm c1:sw v supply = 12 v i load = 0 a figure 45. pulse skip c1:sw v supply = 12 v i load = 0 a figure 46. skip cycle c1:sw v supply = 12 v i load = 0 a figure 47. loop response c1: v supply , c2: inductor current v supply = 12 v c3: v out , c4: ss i load = 0 a figure 48. start-up advance information
43 LM5122ZA www.ti.com snvsb54 ? may 2018 product folder links: LM5122ZA submit documentation feedback copyright ? 2018, texas instruments incorporated 9 power supply recommendations the LM5122ZA is a power management device. the power supply for the device is any dc voltage source within the specified input range. 10 layout 10.1 layout guidelines in a boost regulator, the primary switching loop consists of the output capacitor and n-channel mosfet power switches. minimizing the area of this loop reduces the stray inductance and minimizes noise. especially, placing high quality ceramic output capacitors as close to this loop earlier than bulk aluminum output capacitors minimizes output voltage ripple and ripple current of the aluminum capacitors. in order to prevent a dv/dt induced turnon of high-side switch, connect ho and sw to the gate and source of the high-side synchronous n-channel mosfet switch through short and low inductance paths. in fpwm mode, the dv/dt induced turnon can occur on the low-side switch. connect lo and pgnd to the gate and source of the low- side n-channel mosfet, through short and low inductance paths. all of the power ground connections must be connected to a single point. also, all of the noise sensitive low power ground connections must be connected together near the agnd pin, and a single connection must be made to the single point pgnd. csp and csn are high-impedance pins and noise sensitive. route csp and csn traces together with kelvin connections to the current sense resistor as short as possible. if needed, place 100-pf ceramic filter capacitor close to the device. mode pin is also high impedance and noise sensitive. if an external pullup or pulldown resistor is used at mode pin, place the resistor close to the device. vcc, vin, and bst capacitor must be as physically close as possible to the device. the LM5122ZA has an exposed thermal pad to aid power dissipation. adding several vias under the exposed pad helps conduct heat away from the device. the junction to ambient thermal resistance varies with application. the most significant variables are the area of copper in the pc board, the number of vias under the exposed pad and the amount of forced air cooling. the integrity of the solder connection from the device exposed pad to the pc board is critical. excessive voids greatly decrease the thermal dissipation capacity. the highest power dissipating components are the two power switches. selecting n-channel mosfet switches with exposed pads aids the power dissipation of these devices. 10.2 layout example figure 49. power path layout advance information controller vin gnd gnd vout inductor c in c in c out c out r sense q h q l place controller as close to the switches
44 LM5122ZA snvsb54 ? may 2018 www.ti.com product folder links: LM5122ZA submit documentation feedback copyright ? 2018, texas instruments incorporated 11 device and documentation support 11.1 trademarks webench is a registered trademark of texas instruments. all other trademarks are the property of their respective owners. 11.2 electrostatic discharge caution these devices have limited built-in esd protection. the leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the mos gates. 11.3 glossary slyz022 ? ti glossary . this glossary lists and explains terms, acronyms, and definitions. 12 mechanical, packaging, and orderable information the following pages include mechanical, packaging, and orderable information. this information is the most current data available for the designated devices. this data is subject to change without notice and revision of this document. for browser-based versions of this data sheet, refer to the left-hand navigation. advance information
package option addendum www.ti.com 18-jul-2018 addendum-page 1 packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish (6) msl peak temp (3) op temp (c) device marking (4/5) samples LM5122ZApwpr preview htssop pwp 24 2000 green (rohs & no sb/br) call ti level-3-260c-168 hr -40 to 125 xLM5122ZA mh LM5122ZApwpt preview htssop pwp 24 250 green (rohs & no sb/br) call ti level-3-260c-168 hr -40 to 125 xLM5122ZA mh pLM5122ZApwpt active htssop pwp 24 250 tbd call ti call ti -40 to 125 (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) rohs: ti defines "rohs" to mean semiconductor products that are compliant with the current eu rohs requirements for all 10 rohs substances, including the requirement that rohs substance do not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, "rohs" products are suitable for use in specified lead-free processes. ti may reference these types of products as "pb-free". rohs exempt: ti defines "rohs exempt" to mean products that contain lead but are compliant with eu rohs pursuant to a specific eu rohs exemption. green: ti defines "green" to mean the content of chlorine (cl) and bromine (br) based flame retardants meet js709b low halogen requirements of <=1000ppm threshold. antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) msl, peak temp. - the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. (4) there may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) multiple device markings will be inside parentheses. only one device marking contained in parentheses and separated by a "~" will appear on a device. if a line is indented then it is a continuation of the previous line and the two combined represent the entire device marking for that device. (6) lead/ball finish - orderable devices may have multiple material finish options. finish options are separated by a vertical ruled line. lead/ball finish values may wrap to two lines if the finish value exceeds the maximum column width. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release.
package option addendum www.ti.com 18-jul-2018 addendum-page 2 in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis.

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